منابع مشابه
An Efficient VLSI Architecture of Viterbi Decoder for DSP Applications
It is well known that data transmissions over wireless channels are affected by attenuation, distortion, interference and noise, which affect the receiver's ability to receive correct information. Convolutional encoding with Viterbi decoding is a powerful method for forward error detection and correction. It has been widely deployed in many wireless communication systems to improve the limited ...
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This paper presents an efficient Low-Power Viterbi Decoder Design using T-algorithm. It implements the viterbi decoder using T-algorithm for decoding a bit-stream encoded by a corresponding forward error correction convolutional encoding system. A lot of digital communication systems incorporated a viterbi decoder for decoding convolutionally encoded data. The viterbi decoder is able to correct...
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It is well known that data transmissions over wireless channels are affected by attenuation, distortion, interference and noise, which affect the receiver’s ability to receive correct information. Convolutional encoding with Viterbi decoding is a powerful method for forward error detection and correction. It has been widely deployed in many wireless communication systems to improve the limited ...
متن کاملAn Efficient Viterbi Decoder Implementation for the ZSP500 DSP Core
This paper describes an efficient implementation of the Viterbi decoding algorithm on the ZSP500 digital signal processor (DSP) core. It starts with an introduction to convolutional coding and Viterbi decoding as a method of forward error correction in communication systems. An introduction to the ZSP500 architecture is followed by a description of special instructions for performing the Trelli...
متن کاملBehavioural Synthesis of an Adaptive Viterbi Decoder
The synthesis of a hardware implementation of a Viterbi decoder from a behavioural specification is discussed. This is applied to a parallelized version of a BCH decoder. A parameterizable high-level VHDL model of the parallel decoder has been developed. Scalability of the parallel decoder in hardware is demonstrated. An extension of this technique to an adaptive decoder is discussed.
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ژورنال
عنوان ژورنال: IOSR journal of VLSI and Signal Processing
سال: 2013
ISSN: 2319-4197,2319-4200
DOI: 10.9790/4200-0234650